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San Jose 
$10/h
1st lesson free!
Verified teacher profile
Response Time 24h
Lessons offered by Brian
  • Individual
The lessons will be held
  • at your home
Taught subjects
  • Academic tutoring
  • High School Entrance Exam
Levels
  • All Levels

Engineer offering math, english and history lessons in San Jose with 5 years experience

Methodology

I have a BA in Mathematics/Economics and a MSEE in Solid State Electronics. I have been
an engineer in the bay area for 35 years. I have helped beginning engineers all throughout
my career and take a individual approach with personal attention. I like to teach math at
any level up to and including high school.

Background

As a graduate student at Clarkson, I was a TA and taught control systems and
electronics, graded papers and helped individual students with course material
and homework for 3 years . As an engineer, I have mentored beginning engineers
in ASIC design for over 30 years.

Rates

Rate for a 1-hour lesson. : $10/h
Lessons offered by Brian
Individual
The lessons will be held
at your home
Taught subjects
  • Academic tutoring
  • High School Entrance Exam
Levels
  • All Levels

Brian's resume

Intel
Santa Clara, CA
Physical Design Engineer

• Accomplished Place and Route of 5 blocks in finfet 10nm using
Synopsys tools for the rtl2gds flow.
• Duties include Synthesis, floorplanning, placement optimization, CTS, routing,
extraction, noise analysis and repair, signoff timing, LVS and DRC.
• Other duties included help to develop a low power flow for icc2 using a wrapper
develped by the power design architect around ptpx. The developers had variable ie merge and prune vector sequential, SPG, use of SAIF, reduced cap mode with threshold of 10ps,

Wipro
San Jose, CA
Physical Design Engineer

• Accomplished for Place and Route of 2 blocks in 28nm using
Innovus tools and Calibre tools for the rtl2gds flow.

• Duties include Synthesis, floorplanning, placement optimization, CTS, routing,
extraction, noise analysis and repair, signoff timing, LVS and DRC.
• Other duties included helping setup a 28nm flow and sdc constraints
using Innovus tools, PTSI and Calibre.

SSI
San Jose, CA
Physical Design Engineer

• Accomplished for Place and Route of 5 blocks in 14nm and 28nm using
ICC and Calibre tools for the rtl2gds flow.
• Duties include floorplanning, placement optimization, CTS, routing,
extraction, noise analysis and repair, signoff timing, LVS and DRC.
• Other duties included helping setup a 28nm flow and sdc constraints
using ICC tools, and PTSI and Calibre.

Intel 7/2016 to 2/2017
Santa Clara CA
Physical Design Engineer

• Accomplished place and route of a 2M gate design in 28nm using ICC tools
for the rtl2gds flow.
• Responsibilities included floor planning, place and route, clock tree synthesis,
extraction noise analysis, power analysis using Redhawk, timing analysis using
Primetime, formal verification using Verplex, DRC and LVS using Calibre.

SSI
San Jose, CA
Physical Design Engineer

• Accomplished place and route of 7 blocks in 14nm using
ICC and Calibre tools for the rtl2gds flow.
• Duties include floorplanning, placement optimization, CTS, routing,
extraction, signoff timing, LVS and DRC..

Intel
Santa Clara CA
Physical Design Engineer

• Accomplished for evaluting 14nm PDK in Genus, Innovus and Tempus.
• Worked on flow in Genus, creating a multi-bit flow. Did comparisons
on various in-house design using Genus. Innovus, Tempus and Calibre.

Qualcomm
Raleigh NC
Physical Design Engineer

• Performed floor planning for the m4m/Istari project. Evaluated grouping options
during placement.
• Performed static timing analysis using PTSI on a Finfet 10nm mixed-signal project. Evaluated and corrected UPF issues on a low power design using mutiple voltage islands
using ICC

Intel 9/2013/to 11/2014
Santa Clara CA
Physical Design Engineer

• Accomplished clock tree synthsis of a 2M gate design in 15nm using RDT
within ICC tools. Scripted to find sync pathes of clock trees
• Responsible for synthesis of a 8M gate design at top level using dc_shell
for a stereo digital sight and sound chip in 45nm. Timing verification was
done using ptsi.
• Responsible for place and route of 2 2M gate and 1 1M gate 45nm blocks
using ICC tools for the rtl2gds flow.
• Duties included floor planning, place and route, clock tree synthesis, extraction,
noise analysis, timing analysis using Primetime, formal verification using Verplex,
and DRC and LVS using Calibre.

AVAGO
Fort Collins, CO
Physical Design Engineer

• Accomplished place and route of six SOC 3M gate 28nm blocks
using EDI tools for the rtl2gds flow.
• Duties included floor planning, place and route, clock tree synthesis, extraction, noise analysis, timing analysis using Primetime, formal verification using Verplex and DRC and LVS using ICV.
.
ALTERA
San Jose, CA
Physical Design Engineer

• Accomplished place and route of a SOC 3M gate 45nm design using ICC tools
for the rtl2gds flow.
• Duties included place and route, clock tree synthesis, routing, extraction, timing analysis, formal verification, DRC and LVS using Calibre.
• Accomplished constraint and timing analysis using GCA and PTSI for a 200M
gate network design in 28nm.
• Scripted IO constraints.



Qualcomm
San Diego, CA
Physical Design Engineer

• Accomplished floor planning of a top level CDMA CMOS test vehicle design
in 9.1_usr2 FE.
• Duties include IO and bump assignment and placement, block placement
placement, clock tree placement and routing, power design, verification.
• Worked closely with R&D implementing new technologies into floor planning.
• Scripted for floor planning of bumps using perl and tcl.
• Ran update timing in Olympus and performed IR analysis and debug in Redhawk.
• Ran regression tests in talus for evaluating updated flow and verified timing in PTSI.
• Performed DRC, LVS and logical verification in Calibre and Verplex for a 3M gate modem design in 28nm.

NVIDIA
Santa Clara, California
Physical Design Engineer

• Accomplished automatic place and route of 7 hierarchical GPU blocks ranging in size of up 4M gates using Talus tools in 40nm CMOS for the rtl2gds flow. Two projects were successfully taped out to TSMC. This included floor planning, timing driven placement, CTS using power centric from Azuro, noise and timing aware routing, timing convergence, noise avoidance using Talus and noise repair using Sequence or Pinnacle tools.
• Final timing analysis and noise analysis was performed using PrimeTime.
• Final Verification was done for logic using Formality, power analysis using Powermeter, and DRC/LVS using Calibre and Hercules.
• Scripted location of diodes in input pins.

Infotech
San Jose, California
Physical Design Engineer

Project lead for a 2M gate multi-media project using First Encounter tools that was successfully taped out to TSMC.
* Accomplished floor planning, place and route, CTS, timing closure, power analysis, DRC and LVS foe the rtl2gds flow.
* Accomplished place and route of various hierarchical blocks in 90nm ranging in size from 500k to 1.5M gates from rtl to gds using First Encounter SOC. This included floor planning of regions, RF and SRAM IP, timing driven placement, clock tree synthesis, post route optimization using NanoRoute's noise avoidance and FE/Celtic's glitch optimization repair, PR timing analysis and noise analysis using Celtic and PrimeTime. Final Verification was done for logic using Formality, power analysis using Voltage Storm, and DRC/LVS using either Assura or Calibre.

* Developed power models for one flow using mcaps to reduce the noise bounce to
Less than 15mV
* Used Cadence’s VXL for schematic and layout editing of digital and analog blocks. Completed one RFID block for low power application using Astro/ICC and design compiler. Multiple gated clocks balanced.
* Work also included balancing 55 clocks in scan and functional mode using Magma tools for a 5M gate low power multi-media application.
* Responsible for power grid design and analysis of a 5M gate design in 90nm using flip chip technology.
* Work also involved automatic place and route flow setup using tcl and FE tools. This included place and route, optimization, CTS, extraction, noise avoidance, repair and analysis, power analysis and IR drop analysis using voltage storm.
* Work also included implementing various high speed blocks in 0.65um technology including place and route, optimization, CTS and timing verification.

AZUL SYSTEMS
Mountain View, California
Physical Design Engineer

Accomplished the place and route of 6 hierarchical blocks ranging in size from 150k gates to 500K gates of a 15M gate/logic with SRAM/RF/TRAM 0.13um CMOS design using First Encounter SOC and Sequence Design tools. This included floor planning of regions, RF and SRAM IP, timing driven placement, clock tree synthesis, post route optimization using NanoRoute's noise avoidance and Physical Studio for setup, hold and glitch optimization repair, PR timing analysis and noise analysis using Physical Studio and PrimeTime. Final Verification was done for logic using Formality, power analysis using CoolTime, and DRC/LVS using Calibre. Final design was successfully taped out to TSMC. Successfully taped out the 90nm version of our first product.
• Scripted in perl power estimation of memories.
.
CROSSLAYER
Fremont, California
Physical Design Engineer

Project lead for the backend of a 5M gate 0.18um CMOS design.
Successfully established a rtl2gds flow for 0.18um CMOS UMC technology
using Silicon Perspective and Astro/ICC tools. This included all aspects of the backend
such as library development, floor planning, clock tree synthesis, place and routing,
back annotation, timing optimization and physical verification. Taped out a
successful 5M gate 6M bits of SRAM 0.18um CMOS design.

EDUCATION

MS Electrical Engineering, Clarkson College, Potsdam, New York
BA Mathematics and Economics, Indiana University, Bloomington, Indiana


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